1. Field of the Invention
The present invention relates generally to a digital audio reproducing apparatus, and more particularly to a control system for deinterleaving memories in digital audio reproducing apparatus.
2. Description of the Prior Art
As is well known in the field of audio equipment, digital recording and reproducing systems utilizing a pulse code modulation (hereinafter simply refered to PCM) techniques have been used for recording and reproducing with high density and high fidelity. The digital recording and reproducing system for audio equipment is referred to as digital audio systems. In the digital audio system, the recording medium used for digitized data which are digitally coded from the analogue information signal are conventional magnetic tapes and discs. Since its many audio characteristics, however, are independent of the quality of the recording medium, the digital audio system is evaluated as being remarkably superior to those of conventional analogue recording and reproducing systems.
An optical compact disc (hereinafter simply refered to as CD), for example, is known as a recording medium on which the audio signal is recorded by PCM. In the recording of PCM data on the CD, an EFM (Eight to Fourteen Modulation) technique is further utilized for the benefit of reproducing the CD so as to extract bit synchronizing signals easily from the recorded PCM data and accurately perform a data slice on a reproduced signal from the CD, which is generally an RF signal since it has a radio frequency, by narrowing a frequency band of the recorded PCM data. The EFM is a technique where the digitized data are divided every eight bits and then modulated in a fourteen bit word data for easily reproducing the CD. Twenty four data words make a frame consisting of five hundred and eighty eight bits together with four P-parity check words P, four Q-parity check words Q, frame synchronizing data bits, control data bits and margin bits. It has been previously proposed to use a so-called cross-interleave technique in a data transmission system that is effective in correcting burst errors. According to this cross-interleave technique, P-parity check words P are provided for error correction to the data words contained in an original arrangement state in the frame, while Q-parity check words Q are provided for error correction to twenty eight data words (except Q-parity check words Q) contained in an arrangement state converted through the cross-interleave technique in a predetermined order.
In the reproducing process, an RF signal or a signal picked up from the CD as a round sinusoidal waveform signal is shaped into a rectangular waveform signal, and then carries out an EFM demodulation, deinterleaving, an error correction and D/A (digital to analogue) conversion in order.
FIG. 8 shows a block diagram of an example of the reproducing section of the digital audio system. In the drawing, a reproduced signal from a CD is supplied to a EFM demodulator 12 through an input terminal 11 after it is shaped into the rectangular waveform and then demodulated to the original eight bits PCM data word from the fourteen bits EFM modulated words therein. The data words are stored into a read/write memory or a random access memory (RAM) 13. A write processing (DAIN) of the data words to RAM 13 is controlled by a clock signal extracted from phase components of the reproduced signal so that the data words written into RAM 13 are affected with jitter according to the irregularities of the disc rotating system. RAM 13 is provided with buffer memory areas necessary for absorbing the jitter.
The data words stored in RAM 13 are read out and supplied into a first error correction processor (refered simply as C1 processor hereinafter) 14 in the order of thirty two words (referred as symbols hereinafter) U0 to U31 which are converted by the cross-interleave technique and then checked for errors on the symbols. C1 processor 14 corrects some error symbols Ui' in the symbols to correct symbols Ui by using P-parity check words P and then writes again the correct symbol Ui into RAM 13 in place of error symbol Ui'. C1 processor 14 has an ability for correcting two error symbols.
The symbols processed by C1 processor 14 are again read out from RAM 13 and supplied into a second error correction processor (refered simply as C2 processor hereinafter) 15 in the order of twenty eight symbols U0 to U27 except Q-parity check word symbols and then checked for errors on the symbols. C1 processor 15 corrects some error symbols Uj' in symbols U0 to U27 to correct symbols Uj by using Q-parity check words Q and then writes again correct symbols Uj into RAM 13 in place of error symbols Uj'. C2 processor 15 has an ability for correcting three error symbols.
After the error corrections at C1 processor 14 and C2 processor 15, correct data symbols stored in RAM 13 are read out again and supplied into an error compensation circuit 16 wherein the data symbols are further processed by a known error compensation technique for any error symbols left uncorrected by C1 processor 14 and C2 processor 15. The word symbols compensated at error compensation circuit 16 are applied to a D/A converter (not shown) through an output terminal 17 connected to error compensation circuit 16.
The deinterleaving is performed by reading symbols Uo-U27 out from RAM 13 with a predetermined delay amount. Symbols U0-U27 are prescribed to have individually the amount of delay 27D, 26D, . . . and 0D, where D equals four times a frame F, i.e., D=4F and one frame F includes thirty two symbols U0-U27. RAM 13 is therefore provided with memory areas capable of storing the longest delay amount 27D.
Now, an example of RAM 13 will be explained, where seven symbols U0-U6 are adopted and the respective delay amounts are assumed as 6F, 5F, . . . and 0F. In this example, RAM 13 has its memory area allocated as shown in FIG. 9. Row H and column V in the drawing respectively mean lower and upper addresses of RAM 13. Write and read operations of a symbol, e.g., symbol U2 are repeatedly made as shown in FIG. 10, wherein letters r and w represents respectively a read address and a write address of symbol U2. Since symbol U2 is assigned from "0" to "4" of lower address H as to its write area, a scale-of-5 downcounter (not shown) is used for an address generator. Count values "0" to "4" of the scale-of-5 downcounter are used as write addresses w as they are, and values given by modulo-5 addition to the count values, i.e., write addresses w. Practically, a scale-of-8 downcounter which is mass-manufactured commercially and easily available is used in place of the scale-of-5 downcounter. In FIG. 10, CN5 represents the count values of the scale-of-5 downcounter (actually a part of the scale-of-8 downcounter), and mod5 means the modulo-5 operation.
Therefore, a circuit diagram as shown in FIG. 11 has been conceived for generating write addresses w and read addresses r for all of symbols U0 to U6 for the example shown in FIG. 9. In FIG. 11, there are provided a group of downcounters 18 and a ROM (Read Only Memory) 19. Downcounter group 18 and ROM 19 are coupled respectively to first and second selectors 21, 30 which are connected to an input terminal 20. The downcounters of scale-of-7 to scale-of-1 respectively generate lower addresses H for writing respective symbols U0 to U6 into RAM 13, while ROM 19 supplies delay amount data of 6F or 0F corresponding to respective symbols U0 to U6.
Input terminal 20 receives data respectively indicating symbols U0 to U6, a read request signal (referred as read signal hereinafter) and a write request signal (referred as write signal hereinafter). Symbols U0 to U6 are applied from EFM demodulator 12, C1 processor 14 and C2 processor 15 in accordance with any stage in the course of the deinterleaving process (see FIG. 8). The read signal and the write signal are applied from a CPU (Central Processing Unit, not shown).
In the write mode of RAM 13 (see FIG. 8), symbols U0 to U6 and the write signal are supplied to input terminal 20. First selector 21 selects a downcounter corresponding to the symbol under operation from downcounter group 18 in response to the write signal. Counts CN7-i of selected scale-of-(7-i) downcounter are supplied to RAM 13 (see FIG. 8) successively as lower addresses H therefor through an adder 22, a modulo operation circuit 23 and a first output terminal 24 in order. (The letter i means any integer of 1 to 6.) At the time, however, modulo operation circuit 23 is deactivated by a controller 25 coupled between input terminal 20 and itself so as to pass therethrough counts CN7-i of selected scale-of-7(7(7-i) downcounter as they are. Controller 25 deactivates modulo operation circuit 23 in response to the write signal supplied from input terminal 20. At the time, moreover, a second input of an AND gate 26 whose first input and output are coupled respectively to second selector 30 and adder 22 is held at a low (L) level. Then AND gate 26 fails to transmit the output of ROM 19 to adder 22 so that adder 22 transmits counts CN7-i of selected scale-of-(7-i) downcounter as they are to RAM 13 (see FIG. 8). Accordingly, counts CN7-i are supplied to RAM 13 as lower addresses H. A decoder 28 coupled to input terminal 20 generates upper addresses V in response to the write signal and supplies upper addresses V into RAM 13 through second output terminal 29.
In the read mode of RAM 13 (see FIG. 8), symbols U0 to U6 and the read signal are supplied to input terminal 20. First selecter 21 selects a downcounter, e.g., scale-of-(7-i) downcounter, from downcounter group 18 in response to the read signal so that counts CN7-i of selected scale-of-(7-i) downcounter are supplied to adder 22. At the same time, second selector 30 provides a delay mount data (6-i)D selected from ROM 19 in response to the read signal to the first input of AND gate 26. The second input of AND gate 26 is held at a high (H) level in the read mode of RAM 13 so as to transmit selected delay data 6-i therethrough. Then adder 22 adds selected delay data 6-i on counts CN7-i of selected scale-of-(7-i) downcounter and then supplies the sum obtained by the addition to modulo operation circuit 23. Modulo operation circuit 23 makes its modulo-5 operation on the sum and then provides its modulo-5 sum output as lower addresses H to RAM 13 through first output terminal 24, while decoder 28 generates upper addresses V in response to the read signal and supplies generated upper addresses V into RAM 13 through second output terminal 29.
However, a conventional deinterleaving apparatus comprised of the previously conceived circuit arrangement as shown in FIG. 11 for generating the write addresses and the read addresses for the RAM are required to have many downcounters in response to the number of symbols. Therefore the structure of the conventional deinterleaving apparatus has been very complicated. And moreover, the conventional deinterleaving apparatus has been expensive because there have been left in the RAM several memory areas unused.